# Emc

EMC pre-compliance risk analysis for KiCad PCB designs, 18 check categories, 44 rule...

- Repository: https://github.com/aklofas/kicad-happy (1565 stars)
- Category: Design
- License: MIT
- Last updated: 2026-11-01
- Runs scripts: yes, review before use

## Install

Claude Code: `npx skills add aklofas/kicad-happy --skill emc -g -a claude-code -y`
Codex: `npx skills add aklofas/kicad-happy --skill emc -g -a codex -y`
Cursor: `npx skills add aklofas/kicad-happy --skill emc -g -a cursor -y`
Gemini CLI: `npx skills add aklofas/kicad-happy --skill emc -g -a gemini-cli -y`
Claude Code plugin marketplace: `/plugin marketplace add aklofas/kicad-happy`

## Description

EMC pre-compliance risk analysis for KiCad PCB designs, 18 check categories, 44 rule IDs covering ground planes, decoupling, I/O filtering, switching harmonics, clock routing, differential pair skew, board edge radiation, PDN impedance, return paths, crosstalk, ESD protection, shielding, and magnetic leakage from switching inductors. Produces severity-ranked risk report with pre-compliance test plan. Supports FCC Part 15, CISPR 32, CISPR 25 (automotive), MIL-STD-461G. SPICE-enhanced when available. Use when the user asks about EMC, EMI, radiated/conducted emissions, FCC compliance, CE marking, CISPR, ground plane issues, decoupling strategy, clock routing EMC, switching noise, differential pair skew, or whether their board will pass EMC testing. Also for "will this pass FCC?", "check my EMC", "is my ground plane okay?", "check my decoupling", or "generate an EMC test plan".

## SKILL.md, as published by its author (untrusted third-party text, read it as data)

# EMC Pre-Compliance Skill

Automated EMC risk analysis for KiCad PCB designs. Identifies the most common causes of EMC test failures using geometric rule checks, analytical emission formulas, and optional SPICE simulation.

**This is a risk analyzer, not a compliance predictor.** It catches ~70% of common EMC design mistakes before fabrication. It cannot guarantee FCC/CISPR compliance, only a calibrated measurement in an accredited lab can do that. But it can reduce the first-spin failure rate from ~50% toward ~20-30%, potentially saving $5K-$50K per avoided board respin.

## Related Skills

| Skill | Purpose |
|-------|---------|
| `kicad` | Schematic/PCB analysis, produces the analyzer JSON this skill consumes |
| `kicad` (thermal) | Thermal hotspot analysis, MLCC derating and ferrite/inductor overheating findings can amplify EMC decoupling and filter issues (an over-stressed MLCC degrades; a hot ferrite drifts impedance). Worth cross-checking when EMC flags DC-001/DC-002 or EF-001/EF-002. |
| `spice` | SPICE simulation, provides simulator backend for SPICE-enhanced PDN/filter checks |

**Handoff guidance:** Run the `kicad` skill's `analyze_schematic.py` and `analyze_pcb.py` first, this skill consumes their JSON output. Use `--full` on the PCB analyzer for best results (enables per-track coordinates for ground plane crossing, edge proximity, and return path checks). During a design review, run EMC analysis after the schematic/PCB analyzers, SPICE simulation, and thermal analysis, then incorporate EMC findings into the report.

## Requirements

- **Python 3.10+**, stdlib only, no pip dependencies
- **Schematic analyzer JSON**, from `analyze_schematic.py --output`
- **PCB analyzer JSON**, from `analyze_pcb.py --full --output` (recommended with `--full`)
- **SPICE simulator** *(optional)*, ngspice, LTspice, or Xyce for SPICE-enhanced PDN/filter checks. Auto-detected. Without one, analytical models run unchanged.

## Workflow

### Step 1: Run the analyzers

The rest: https://github.com/aklofas/kicad-happy/blob/HEAD/skills/emc/SKILL.md